The present invention relates to the semiconductor integrated circuits chip manufacturing and more particularly to a method of forming metal contact pads and contact terminals on semiconductor chips for purposes of face-down bonding to the metal conductors of a metallized carrier such as a metallized ceramic (MC) substrate.
Solder reflow is also known under the generic name of "flip-chip" or Controlled Collapse Chip Connection (C4) technique. The latter is described in particular in U.S. Pat. No. 3,401,126 and 3,419,040 assigned to the assignee of the present invention. According to the C4 technique, the important point is the formation of contact terminals on the semiconductor chip contact sites, each consisting of a metal pad surmounted by a Pb-Sn solder ball. The C4 technique also relies on the formation of solder joinable sites on the metal conductors of the MC substrate. The solder joinable sites are surrounded by non-solderable barriers so that when the solder of the solder joinable sites and of the chip contact terminals melt and merge, the surface tension holds the semiconductor chip by solder columns, as if suspended above the MC substrate. After cooling, the chip is firmly maintained face-down on the metal conductors by these very small, closely spaced solder column interconnections.
With the development of the integrated circuit semiconductor chip technology, the size of individual active and passive devices has become very small causing the number of devices in a chip to increase dramatically. The size of modern chips tends to increase too. This trend will continue and place an increasingly higher demand on the density of contact terminals for input/output connections and the overall number thereof. An advantage of solder reflow joining as practiced in the C4 technique, is that I/O contact terminals can be distributed over substantially the entire top surface of the semiconductor chip, which is more commonly known as the bonding area, therefore allowing an efficient use thereof.
FIG. 1 illustrates a schematical cross-sectional view of a portion of a standard semiconductor chip structure referenced 10 provided with a typical multilevel metallurgy. The fabrication of the chip is entirely conventional and may be completed by any of a number of known processes. For sake of illustration, the chip may be fabricated using CMOS technology with three layers of metal interconnection wiring and I/O contact terminals using the afore-mentioned C4 technique. As shown in FIG. 1, the chip structure has a semiconductor body 11 of one conductivity type with an insulating layer 12, typically of silicon dioxide (SiO.sub.2) on the upper surface thereof. Formed in the body 11 is an active diffused/implanted region 13 of an opposite conductivity type. The first level conductive pattern comprises metal lands 14. One land 14 is in contact with region 13 through an opening in layer 12. Other portions of the conductor pattern 14 extend on the surface of layer 12. An insulating layer 15, e.g. SiO.sub.2, glass or quartz, is formed over layer 12 and metal lands of the first level conductive pattern. Metal lands 16 of the second level conductive pattern are formed on insulating layer 15 and contacts the first level metallization through a via hole. Typically metal lands are made of aluminum Overlying insulating layer 17 and metal lands 18 of the third level conductive pattern is a new passivating layer 19. At the top surface of the chip structure, a composite assembly comprised of a contact pad 20 and a solder ball 21 makes an electrical contact to metal land 18, through a contact opening in passivating layer 19. This composite assembly forms the so-called chip contact terminal 22.
FIG. 2 is an enlarged view of the top part of chip structure 10 of FIG. 1 including contact pad 20 and solder ball 21. As illustrated in more details in FIG. 2, where said top part referenced 23 forms the base structure, contact pad 20 is comprised of a lower chromium (Cr) layer 24, an intermediate copper (Cu) layer 25, and an upper gold (Au) layer 26. A chromium/copper overlap layer is generally inserted between layers 24 and 25. More details on that particular Cr-Cu-Au contact pad structure can be found in EP-A-0061593 assigned to the the present assignee These sandwiched layers form the so-called ball limiting metallurgy (BLM). However, other metal combinations (e.g. TiW, Cu, Au) can be used as well, provided they have the desired adhesion and diffusion barrier properties, to avoid metal corrosion problems. The general pad shape is circular, but different shapes can be envisioned.
Originally, in the 1960's, when the C4 technique was invented, the three metal layers, forming the ball limiting metallurgy of FIG. 2, were sequentially deposited by vacuum evaporation through an apertured molybdenum mask. However for advanced 125 mm semiconductor wafers a typical configuration consists of 27.times.27=729 contact pads arranged in a matrix with a pitch of 100.times.230 .mu.m and a pad diameter of 100 .mu.m, the use of molybdenum masks that are 100 .mu.m thick is infeasible. Producing more contact pads means producing more holes of smaller diameter (e.g. 75 .mu.m) in the mask, and therefore implies reducing the mask thickness to less than 75 .mu.m. This results from the double-side etch process that is conventionally used to create the holes. Unfortunately, such a thickness is unacceptable because the mask would warp during the evaporation step. Only photolithographic processes appeared to be able to solve this acute problem. Two different variants have been investigated so far to produce the contact pad structure 20 of FIG. 2, the lift-off technique and the sub-etch technique, which are both illustrated in FIG. 3.
Now referring to FIG. 3AA, in the lift-off technique, a photoresist layer PR is applied onto the base structure 23 baked for hardening, then exposed to UV light through a mask (not shown) to make soluble the unexposed portion of layer PR. The soluble portions of the photoresist layer PR are removed in a development bath. As shown in FIG. 3BA, the resist aperture has a typical negative profile. This necessitates the use of complex photoligraphic techniques such as MIRP (Modified Image Reverse Process). Next, metal layers of Cr, Cu, and Au respectively referenced 24, 25 and 26 are blanket deposited in sequence in a vacuum evaporator. The remaining portions of the photoresist layer PR are dissolved in hot N-methyl-pyrrolidone (NMP) and the metal located thereupon is lifted off leaving the metal contact pad structure 20 of FIG. 3C.
Alternatively, the metal contact pad structure may be formed, according to the so-called metal sub-etch technique, that is illustrated in FIGS. 3AB and 3BB. Turning to FIG. 3AB, first, the three metal layers of Cr, Cu, Au referenced 24', 25' and 26' are sequentially blanket deposited onto the base structure 23 in a vacuum evaporator. The contact pad will now be defined by standard photo-lithography. To this end, a photoresist layer PR' is applied onto the base structure. The resist layer PR' is exposed to UV light through a mask (not shown), then developed as illustrated in FIG. 3BB. The remaining portions of the photo resist layer that are insoluble in the development bath are used as an in-situ mask to remove the exposed underlying metal layers by chemical etching, thereby defining the metal contact pad structure 20 as shown in FIG. 3C.
At this stage of the process, irrespective the variants used to form the contact pad structure 20, solder balls are formed. The technique described in U.S. Pat. No. 3,458,925 assigned to the present assignee is still appropriate. To this end, a suitable mask, as of molybdenum (not represented), having holes therein corresponding to and somewhat larger than the contact pad structure is placed over the chip structure 10 so that the holes of the mask are aligned with the contact pads. A layer 21' of 95% lead-5% tin solder, is then evaporated through the mask holes. However, other solder compositions may be used as well. Prior to reflow, the typical solder bump or mound 21' that has just been formed, completely covers the contact pad structure 20 and the surrounding portions of the passivating layer 19 at the vicinity thereof as shown in FIG. 3D. After the solder evaporation is completed, the mask is removed, and the chip heated to reflow the solder, which as it melts, it gradually dewets the surface of the passivating layer, and draws-up into the desired ball configuration 21 on top of the contact pad structure 20 (FIG. 3E). After completion of the above described process, the chip is then ready for flip-chip or face-down bonding to a supporting metallized ceramic substrate in accordance with the various techniques of the prior art.
Both afore-mentioned variants have inherent limitations and/or drawbacks which make them non-satisfactory for use in the manufacturing lines.
In the lift-off technique (FIGS. 3AA & 3BA), the first concern is the poor adhesion of the metal layers forming the contact pad to the aluminum land underneath, because the maximum temperature during vacuum evaporation must be less than the resist bake temperature (e.g. inferior to 100.degree. C.). In addition, the lift off technique implies the use of complex photo-lithographic steps (e.g. MIRP) to produce the negative profile in the apertures. Finally, there is a huge quantity of metal to remove because the ratio between the remaining metal surface after aperture completion and the wafer surface is extremely high, about 98%. As a consequence, the lift-off technique produces metal residues that are known to be a yield detractor. In the metal sub-etch technique (FIGS. 3AB & 3BB), the main concern is the remaining metal residues still because of the important etched quantity of metal. The problem is even more acute in this case, when compared to the lift-off technique, because the metal layers adhere well to the surface of the wafer.
In addition, in both variants, the highly desired step of RF cleaning using Argon (Ar) ions is a recommended initial process step to improve contact resistance, because Ar+ ions etch-back the native oxide that spontaneously forms on the parts of the metal lands that are exposed before contact pad formation. In the metal sub-etch technique, this RF cleaning step is performed prior to metal evaporation. As a result, the Ar+ ion bombardment is effected on the whole surface of the wafer so there is a risk of displacing or activating sodium ions (Na+) in the thin oxide layer forming the gate dielectric of FETs. These ions, can modify the amount of charges in the oxide layer with well known inconveniences as to the threshold voltages of FETs. In the lift-off technique, this RF cleaning step is not possible at all, because of the low temperature that is required to bake photoresist layer PR. The ion bombardment is known to heat the wafer at a temperature (about 150.degree. C.) that would cause photoresist layer PR to flow.